The present invention relates generally to low voltage interconnect techniques and, more particularly, to low voltage signaling systems and methods for integrated circuit devices.
Power consumption on interconnect lines is a significant contributor to the total power in high performance computing and many other applications. On chip data and clock lines consume significant power over a typical distance. Power consumption of off-chip input/output (I/O) lines such as, for example, those connected to DRAM modules could consume about 30%-70% of the total system power. For the highest speed communications, a high-speed serial link consumes even more power per line.
Current mode circuits are commonly used in both the drivers and receivers for achieving high speed transmission rates (e.g., about 6 gigabytes per second (Gb/s) to 15 Gb/s). Such circuits dissipate even higher power than CMOS drivers due to the constant flowing current. The active power in these off-chip connections is given by the expression:P=CV2f
where C is the interconnect capacitance, V is the operating voltage, and f is the frequency at which the connection is operated. Most of the energy is thus consumed by charging and discharging the large capacitive load on I/Os.